The present invention relates to a logic circuit and, more particularly, to a logic circuit having a bipolar CMOS configuration in which bipolar transistors are provided at its output portion.
A logic circuit having a bipolar CMOS configuration has been known, in which bipolar transistors are provided at its output portion through which the charging and discharging of load capacitance of the next stage is conducted.
In a logic circuit having such bipolar CMOS configuration, the bipolar transistors which have larger driving capability than that of MOS transistors are used for the charging and discharging of the load capacitance of the next stage so that, in the case where the amount of the load capacitance at the next stage is large, it is possible to effect the charging and discharging at a higher speed than in a logic circuit with a simple CMOS configuration thereby enabling to achieve a high speed operation of the circuit. An example of such conventional logic circuit having a bipolar CMOS configuration is shown in FIG. 1 and the details of the arrangement thereof and the problems involved therein are fully explained later before the explanation of some preferred embodiments of the present invention.